搜索资源列表
spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
spi slave
- SPI 接口的VHDL和Verilog实现。slave模式
slave_spi_ctrl.rar
- SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集,SPI control course code
SimpleSpi
- SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.
SPI_TEST
- The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave d
spi_slave
- spi slave 8bit address 1bit r/w 7bit number data
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
SPI_vrilog
- SPI接口源码,语言vrilog,包括MASTER和SLAVE-SPI interf for vrilog.
spi_slave
- SPI slave source code
spi_slave
- Simple SPI slave with MOSI MISO SCLK SS signals
conjoined
- SPI protocol: Serial Periphral Interface with both slave and master incorporated-SPI protocol: Serial Periphral Interface with both slave and master incorporated
l1ghVhVI
- The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
spi
- Altera Cyclone SPI-slave vhdl module
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
spi_final_presentation
- Implement SPI Master and SPI Slave cores (VHDL) Implement Master and Slave hosts (VHDL) Verify the entire design (SystemVerilog)
spi_slave_test
- 实现spi协议的从机代码，亲测可用。按照字节接收，发送可以实现一次发送19字节，可按照需要更改。(The implementation of the code of the SPI slave protocol is available. By byte received, sending can be sent to send 19 bytes at a time, which can be changed as needed.)
VHDL_SPISLAVE
- spi-slave通信的vhdl实现及其仿真(VHDL implementation of spi-slave communication)
spi
- 利用VHDL在FPGA内实现SPI总线的主从控制器设计(SPI Master and Slave Controller)
spi_slave
- 使用VHDL语言写的程序，利用SPI协议实现串并转换电路(Programs written in VHDL language and series-to-parallel conversion circuit implemented by SPI protocol)