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树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
sqrt32
- verilog源代码，用于开根号计算（32位）-sqrt32.v sqrt of 32-bit integer, Verilog source
sqrt
- it is a sqrt module ,with test bench.
sqrt
- 实现任意位数的开方算法，但是不是浮点的算法，-Square root algorithm for arbitrary digit, but not floating-point algorithm, thanks
pre_norm_sqrt
- 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
ref-sqroot
- 这是用于VHDL的开方运算，大家试试看，能不能好用-sqrt
sqrt
- This zip file contains the verilog source code for square root calculation and its test bench
sqrt32
- sqrt32.vhdl unsigned integer sqrt 32-bits computing unsigned integer