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ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
ads7825
- use this source code for interface to adc ads7825
vhdlcode
- VHDL code in ISE (for collecting the ADC samples from kit and for viewing final output)
ADC_AMP
- VHDL code for ADC on Spartan 3E starter kit
adcterbaru
- VHDL code for ADC Xilinx Spartan 3E
decimator
- Digital filter in delta-sigma ADC. But only work for RTL code now. Still have bugs in gate-level simulation.
ADC_TLC549
- 实现ADC转换的VHDL代码，利用计数器分频产生1MHz的频率，在此频率下，读取八位的AD数据并存储供处理使用，根据实际需要转换成模拟电平。-ADC conversion of the VHDL code, the use of counter divider to generate a 1MHz frequency, frequency, read eight of the AD data and stored for processing, according to the actual n
DACtest
- Spartan 3E - DAC- VHDL. It is a vhdl code for Xilinx Spartan 3E fpga to run ADC and AMP on the board via SPI interface.
FDK
- LCD1602控制VHDL代码，带有ADC和DAC采样，以及原理图和PCB版图供参考-LCD1602 control VHDL code, with ADC and DAC sampling, as well as schematic and PCB layout for reference
adc
- vhdl code for analog to digital conversion
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
amp_adc
- VHDL code for ADC - Spartan 3e
ADC
- VHDL spurce code for the main configuration of an ADC converter already wornking
AdcInterfaces
- A VHDL Code for ADC Interfaces in FPGAs
AdcInterfaces
- A VHDL Code For ADC Interfaces
adcdac_modify
- ADC-DAC VHDL Working code for Spartan 3/3E FPGA device
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
src
- Spartan-3E. Working VHDL code for amplifier LTC6912, adc LTC1407A-1, dac LTC2624. Archive includes vhdl files and ucf file with comments. Create new project add files and it will be to work.