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equlizer
- 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integra
DDSforsinandcos
- 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
link_port-v1[1].1.0
- 用于测试ADI的TS201与FPGA之间通信的LINK程序，压缩文件内包括VHDL和Verlog代码。-ADI is used to test the communication between the TS201 and the FPGA' s LINK program, compressed file to include VHDL and Verlog code.
TS201_LINK_TRANSFER
- Ts201 link port verilog
CPU
- quartus7.2下以VHDL编程，分为多个模块，在链接原理图中编译。-quartus7.2 next to VHDL programming is divided into multiple modules, compile the schematic in the link.
SPI_TEST
- The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave d
micro-UARTsource_V
- UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。-UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allo
pcie_vera_tb_latest.tar
- FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number
1
- Avalon总线的pwm定制，在niosII下定制了PWM通过avalon总线链接到niosII上，绝非一般的实验，应用在实际的工控项目中。-Avalon bus pwm custom, under the custom of the PWM in the niosII by avalon bus link to niosII on the experiment in general not applied in real industrial control projects.
hdlc_1
- 高级链路控制的HDLC发送，写的还行，需要使用93版本的VHDL格式-Advanced Link Control HDLC to send, write that still need to use the 93 version of the VHDL format
MAC_Transceiver
- MAC(以太网媒体访问控制)是以太网IEEE 802.3协议规定的数据链路层的一部分,使用FPGA替代ASIC,实现以太网MAC功能非常实用。能够实现硬件系统多路多端口的以太网接入,并在自行开发需要以太网接入的嵌入式处理器设计中得到应用。具体探讨以太网MAC的功能定义,使用FPGA实现以太网MAC的方法,对以太网的相关应用设计具有指导作用。 -MAC (Ethernet Media Access Control) is a protocol under the IEEE 802.3 Ethe
mentor_all
- lattice fpga solution for 7:1 DESERIALIZATION INTERFACE ,LIKE FAST LINK, CAMERA LINK.
vhdl
- 当接收到一个信号(D_start)时，开始计时，再收到另一个信号(D_stop)时，计时结束，得到计时时间A，然后将时间A与给定时间B进行比较，如果小于时间B,程序结束，进行下一环节(LED)，否则返回重新等待计时(cnt:=0)-When receiving a signal (D_start), the start time, and then received another signal (D_stop), the time the end of time by time A, then
018vhdl-TTL
- camera link 借口电路的差分信号转换-camera link pretext differential signal conversion circuit
CameraLink-source-code
- 基于FPGA的多路CameraLink数据的发送和接收程序源码-FPGA-based multi-CameraLink data sent and received program source code
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
A-Simplified-VHDL-UART
- In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this
VHDL
- 带有CDR和曼彻斯特编解码的串行接口，代码编译仿真成功过-Control Link Serial Interface with Manchester and CDR
16QAM-Modulation-VHDL-source-code
- This page of VHDL source code covers 16QAM modulation vhdl code and provides link to QQAM modulation basics.
2-bit-parallel-to-serial-conversion-VHDL-source-c
- This page of VHDL source code covers 2 bit parallel to serial vhdl code and provides link to 2 bit serial to parallel conversion.