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Viterbidecoder
- 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
viterbidecoder
- 提供实现了（2，1，7）卷积码的维特比译码的源程序，采用了最大似然算法，介绍了软判决维特比译码算法过程的三个步骤：初始化、度量更新和回溯译码。-for achieving a (2,1,7) Convolutional Codes Viterbi decoding of the source, using the maximum - likelihood algorithm, introduced a soft-decision Viterbi decoding algorithm of the
viterbidecoder
- 2，1，7卷积码的viterbi译码算法的FPGA实现，内容详细，而且附带源代码。
ViterbiDecoder
- 维特比译码，来自现代通信系统matlab-Viterbi Decoder, from modern communications systems matlab
ViterbiDecoder
- this a descr iption viterbi decoder-this is a descr iption viterbi decoder
viterbidecoder
- viterbi decoder that use in communication
viterbidecoder
- viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
viterbidecoder
- 移动通信系统中维特比译码器的硬件实现!j基于FPGA的有关编程代码-viterbi
ViterbiDecoder
- Viterbi decode in VHDL
ViterbiDecoder
- 卷积码Viterbi译码，包括软判决和硬判决，别人上课的程序-Convolutional code Viterbi decoding, including soft decision and hard decision, others school programs