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verilog实现FSK
- 用verilog语言,采用dds技术实现的FSK
verilog dds 正弦输出
- verilog 编写
基于FPGA的直接数字频率合成器(dds)设计
- 基于FPGA的直接数字频率合成器(dds)设计 (源程序),FPGA-based direct digital synthesizer (dds) design (source code)
dds(heli).rar
- dds用verilog 实现,可以实现方波、正弦和三角,dds using verilog realized, can be square wave, sinusoidal and triangular
dds.rar
- FPGA控制AD9854的源文件,verilog,附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
dds
- verilog 硬件语言实现dds,使用ise11.1和modelsim se6.5仿真测试-verilog hardware language dds, using the simulation test ise11.1 and modelsim se6.5
dds
- dds文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "verilog"文件夹内,是用verilog语言编写的 FPGA 程序.-dds program folder, complete direct digital frequency synthesis function, sine, triangle, square
dds
- 基于dds原理的正弦信号发生器。用verilog语言实现,功能强大。-dds based on the principle of sinusoidal signal generator. Using verilog language and powerful.
FPGA-dds
- 在FPGA内,以查表方式实现频率直接合成器(dds)功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (dds) feature. verilog source code
dds_verilog
- verilog dds 在发生正弦波时,很好的参考代码-verilog dds
dds-design
- fpga实现dds,实现任意波形输出信,设计代码verilog-dds fpga realization
dds
- this a code for dds in verilog-this is a code for dds in verilog
dds
- dds文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "verilog"文件夹内,是用verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
dds
- 基于verilog的dds设计,已经经过调试,可直接使用-dds of verilog-based design, has been testing can be used directly
dds
- 同时用verilog 语言编写dds原代码用于生成正余弦波,并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
dds
- 在quartus下的dds设计,verilog语言,可以产生正弦波、三角波、方波等,频率可调。-Under the dds in quartus design, verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
dds
- dds数字式频率合成器 利用verilog实现,有modelsim仿真图-dds digital frequency synthesizer using verilog realization, modelsim simulation diagram
dds
- dds数字频率合成的verilog代码,附有正余弦查找表等-dds digital frequency synthesis verilog code, with a cosine look-up table, etc.
dds-in-verilog
- verilog编写基于FPGA的dds实现,内含源代码,希望对大家有所帮助。-dds in verilog FPGA-based implementation, including source code, we want to help.
verilog-dds
- 用verilog实现的dds,直接频率合成器,相位可调。-verilog dds generator