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Verilog DHL教程.zip
- Verilog DHL教程
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Verilog DHL教程
- Verilog DHL教程-Verilog DHL course
digital-clock
- 该数字钟论文是我用了一周的时间，采用Verilog DHL语言设计， Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
arm7verilog
- ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
ff_const_mul
- 常系数有限域乘法器，verilog DHL源码-Constant coefficient finite field multiplier, verilog DHL source
X-HDL
- 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
ADDER
- verilog DHL编写的一位全加器，编译通过。稍作修改便可编程任意位加法器。-verilog DHL write a full adder, compiled by. Slight modifications can be programmed any adder.
L-CLA20_20-code.
- DHL CLA20_20 development with the Verilog bit ahead carry adder code.
AC PROJECT DHL DOC
- ac project source code for beginner