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filter 代码
- 用verilog实现滤波器的功能，通过软件综合仿真，在利用FPGA实现-using Verilog filter function to achieve through integrated simulation software, the use of FPGA
DDC.rar
- 个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR,DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
fir_hdl.rar
- 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。,Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
Code_for_MedianFilter33.rar
- 3x3中值滤波器的FPGA实现(VERILOG),3x3 median filter FPGA implementation (VERILOG)
filter_verilog.rar
- 用verilog实现的低通滤波器，输入输出精度为64位，并附有测试程序。,Use verilog to achieve a low-pass filter, input and output accuracy of 64, together with testing procedures.
fir.rar
- fir滤波器，Verilog语言写的，容易看懂,fir filter, Verilog language written in easy to understand
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
18a
- 匹配滤波器设计，VERILOG实现的，比较好的哦-Matched filter design, VERILOG implementation, and better oh
filter
- 如何利用verilog设计数字滤波器 包含低通滤波器,带通滤波器,高通滤波器.-how to design a digit filter with Verilog
fir_lms
- 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
median
- 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
verilog.DA.FIR..
- 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
Verilog
- 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
FIR
- FIR filter using verilog code
3-3-median-filter
- verilog编写的适用于fpga的3x3模板中值滤波-verilog fpga prepared for the 3x3 median filter template
digital-filter
- Verilog语言综合的固定频率的数字滤波器，用于滤除夹杂在固定频率信号上的杂波信号，包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
filter
- 数字滤波器的verilog语言程序，为双精度的滤波器，可以实现10k低通滤波-verilog filter
hp and lp filter
- hp and lp filter verilog code..
fir filter design
- FIR FILTER DESIGN IN VERILOG ON FPGA
LMS filter
- lms filter on verilog filter and synthesizable on xilinx