搜索资源列表
FPGA_GPS_C_A
- 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。
GPS去载波verilog实现
- 该源码用verilog实现gps信号的去载波过程
PcodeGeneration
- 在ModelSim或其他支持Verilog语言编译的环境中仿真可得GPS的P码及与卫星数据码调制后的波形，其中一个为源程序，另一个为测试程序-ModelSim or other support in the language Verilog simulation environment to compile available GPS P-code and code of satellite data after the modulation waveform, one for the sour
ca_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number,
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
c_a
- GPS中C/A码产生简单的Verilog逻辑产生-GPS in the C/A code generated simple logic generated Verilog
GPSNaviDataGen_4ch
- 基于verilog语言的ＧＰＳ模拟源代码，代码为４颗星，包含噪声信号。-GPS-based Analog Verilog language source code, code for the four stars, including the noise signal.
GPS
- 用verilog 编写的gps系统调制解调器，很大很实用-Gps system prepared with verilog modem, very very useful
gps
- Implement the GPS module time detection function via verilog language.-gps fuction module implemented in xilinx FPGA
CODE_GEN
- 北斗、GPSC/A码生成器的verilog ，输出速率可调，使用verilog编写- FPGA-based GPS receiver complete code of the spreading code generator design using verilog language
BCH_EN
- 基于FPGA的GPS/BD信号发生器中BCH编码发生器模块，使用verilog编写- FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
NAVI
- 基于fpga的GPS导航数据发生器，使用verilog编写- Fpga-based GPS navigation data generator, using verilog write
code_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。--This program generates Verilog GPS satellite navigation signals for C/A code, the input signal with a clock, clock enable, reset, given the satellite number, the ou
yuandaima
- 以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境-GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II
CAMA
- 基于Verilog语言的GPS卫星PRN1的导航伪码的产生，简单易懂，代码简单。-Generates Verilog language PRN1 GPS satellite navigation based on pseudo-code, easy to understand, simple code.
GPS_TX_RX_VERILOG
- GPS Tx RX verilog 19-GPS Tx RX verilog 1988
GNSSCodeGenerator
- 用于产生GPS信号的verilog语言程序，已经经过调试通过-GNSSCodeGenerator using verilog
quiz 1
- Radix 2 fft in matlab and verilog.