搜索资源列表
rng
- verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的
伪随机序列
- 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and ci
lfsr
- 此实验介绍了伪随机序列的产生原理，并用verilog语言将其编码实现，有详细的代码备注-This experiment introduces the principle of pseudo-random sequence and its encoded with the verilog language implementation, a detailed code Notes
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
lfsr
- 用LSFR实现计数功能，可以减少对寄存器和少一个加法器，涉及verilog的人来说-Used to achieve LSFR counting functions, can be reduced to a few registers and adders, the people involved in Verilog
profiles
- source code of counter,ram,lfsr etc
lfsr.v.tar
- linear feedback shift register for generator in verilog code for random sequence generation.
BIST
- A simple BIST in VHDL. It contains a LFSR with an SISR.
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
lfsr
- linear feedback shift register verilog code
lfsr
- simple PRBS generator using verilog hdl
LFSR
- practical example using verilog and vhdl by xilinx
verilog-lfsr-updown-counter
- Verilog 8 bit LFSR Up-Down Counter
LFSR
- Verilog code for an 8-bit LFSR
LFSR
- 这是基于FPGA开发板NEXTS3的一个verilog程序，是一个线性反馈移位寄存器LFSR,可用来生成伪随机数-This is based on the FPGA development board NEXTS3 a verilog program, is a linear feedback shift register LFSR, can be used to generate pseudo random Numbers
hidejj
- 实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
pseudo_random
- 基于vivado Verilog的伪随机数发生器，采用LFSR算法，并对其进行了升级，使用反馈级联的思想，从最大周期为2^n提升为原来的3-5倍(Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the
lab2B(4)LFSR
- 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)
BIC
- this project for adaptive schme techniques by using LFSR design projects