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Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
fibonacci_matlab_verilog
- 使用Matlab和Verilog实现fibonacci序列，包括源代码和testbench-use matlab and verilog to realize fibonacci sequence,including source code and testbench
feibonaqi
- 斐波那契数列，用VErilog语言实现非常好-Fibonacci sequence, using VErilog language is very good ha ha ha ha ha ha ha
fibonaccicode
- verilog code for fibonacci codes
fibonacci
- Fibonacci in Verilog HDL
RAM
- 用verilog实现了IP核的使用，例化了一个RAM，用来进行读写操作，另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
New folder
- verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.