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verilog for uart
- 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips.
xapp622.zip
- 644 MHz SDR LVDS 发射器/接收器(verilog and doc),644-MHz SDR LVDS Transmitter/Receiver
up_buhuo
- 这是一个VERILOG接收端捕获模块，扩频码32倍，可以检测到相关峰-This is a VERILOG receiver capture module ,the spreader is 32,it can test the correlation peak
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
FPGA_based_infrared_receiver_module
- 基于FPGA的红外接收模块，内含代码，采用VERILOG编写。-FPGA-based infrared receiver module, containing the code prepared by the use of Verilog.
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
ddc
- 随着数模转换器硬件的快速发展和DSP处理能力及处理速度的逐步提高，软件无线电技术在商用和军用无线电通信领域也越来越显示出其强大的吸引力。本文研究的高速中频采样和数字下变频技术是目前蓬勃发展的软件无线电领域的两项关键技术。-As advances in technology provide increasingly faster and less expensive digital hardware, more of the traditionally analog functions of a
Receiver
- UART Receiver Verilog Code
DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
Receiver
- 基于802.11a的OFDM基带硬件设计的verilog代码，在Xilinx ISE环境下实现-The OFDM-based 802.11a baseband hardware design of the verilog code, in the Xilinx ISE environment to achieve
Channel_Equalizer
- 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
Sampling_Frequency_Synchronization
- 802.11a接收机的采样频率同步源码，verilog语言的-802.11a receiver sampling frequency synchronization source, verilog language
qpsk_relate
- QPSK相关接收机及匹配接收机的verilog实现-QPSK correlation receiver and matching receiver verilog implementation
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
RS422_receiver
- UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
Receiver
- OFDM通信系统接收端完整verilog代码-OFDM communication system receiver complete verilog code
verilog
- 这是一本介绍verilog语言的书籍，verilog语言应用于FPGA，可实现诸多实时处理模块，例如实时OFDM发射机和接收机的制作-verilog for FPGA，real time OFDM Transmitter and receiver
serialsimulationreciever
- serial simulation receiver in verilog
Receiver_spartn6_v1
- Implement design of UART receiver in verilog