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CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
ahb_ram
- AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such
AHB_slave-ram
- AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
ahb_slave_ssrw
- 通过AHB总线简单访问register/RAM 的verilog 子模块 ssrw stands for simple single read write.- submodule used for simple configuration register/RAM accesses ssrw stands for simple single read write.
AHB_paper
- AHB 总线规范是 AMBA 总线规范的一部分。AMBA 总线规范是 ARM 公司提出的总 线规范，被大多数 SoC 设计采用，它规定了 AHB（Advanced High-performance Bus）ASB （Advanced System Bus）APB(Advanced Peripheral Bus)。AHB 用于高性能、高时钟频率的 系统结构，典型的应用如 ARM 核与系统内部的高速 RAM，Nand Flash，DMA，Bridge 的 链接。APB 用于连接外部设
ahb_ebc
- Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
ARM_SOC
- ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker