搜索资源列表
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
ram_top
- arm ahb slave bus sram ip in verilog
bus_ahb_to_sram
- amba ahb to sram verilog
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
ahb_sram
- amba总线的ahb到sram的接口，Verilog代码，还算详细，算是不错的资料。(The AHB to SRAM interface of the AMBA bus)
ahb_task
- ahb接口的sram做读写测试的读写时序(SRAM of the AHB interface for reading and writing tests)
ahb_sramc
- 基于AHB总线的sram控制器，带有memory bist(SRAM controller based on AHB bus)
svtb_ahb_sram
- 一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)