搜索资源列表
GATE
- 楼宇可视对讲门口机C语言源程序，以及AT89X系列芯片的祥细资料。-source code of interphone/door entry system and document of AT89X
NiosII_implementation_in_CCD_C
- The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, cur
Log_Shifter_Gate_Level_Design
- Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
Clock_Gating
- 本文重点详细讲述了gate clock的用法和设计-In this paper, the focus of a detailed account of the gate clock usage and design
74
- 7400 QUAD 2-INPUT NAND GATES 与非门 7401 QUAD 2-INPUT NAND GATES OC 与非门 7402 QUAD 2-INPUT NOR GATES 或非门 7403 QUAD 2-INPUT NAND GATES 与非门 7404 HEX INVERTING GATES 反向器 7406 HEX INVERTING GATES HV 高输出反向器 7408 QUAD 2-INPUT AND GATE 与门 7
and_gate
- And gate testbench, testbench to simulate and run in modelsim
pacb_speed
- 使用PACB方式测试脉冲的程序，主要和光电门一起使用，用于测速-PACB at testing the use of pulse procedure, used in conjunction with the principal and optical gate for speed
AND
- vhdl code for AND gate
2
- systemc 实现与非门，这里是步骤和代码-NAND gate implementation systemc, here is the steps and code
Design-AND-gate
- 通过应用QUARTUSII开发软件对与门的设计（二输入）和D触发器的设计。 -QUARTUSII development through the application of software and door design (two inputs) and the D flip-flop design.
and
- this is vhdl code for and gate
and
- and gate implementation
test--and-gate-or-gate-not-gate
- 检测与门、或门、非门等门电路芯片是否正常的程序-Whether the normal procedure of detect AND gate, OR gate, NAND gates gate circuit chip
AND
- this "AND" gate implementation in VHDL-this is "AND" gate implementation in VHDL
AND-gate
- fpga verilog入门经典系列：与门。-and gate
AND-Gate-Using-Behavioral-Modeling---iblocks_file
- and gate design in verilog
and-gate
- programming of and gate
and
- and gate implemented in fpga
HEB AND
- AND GATE SIMULATION COD IN MATLAB BY NEURAL NETWORK TO HEB ALGORITM
guid
- IC TESTER CODE for OR GATE, AND GATE, NOT GATE