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AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
pci_arbi_quicklogic
- PCI 仲裁代码/ PCI BUS ARBITER //WRITTEN BY MARIA GEORGE `include "c:\pasic\spde\data\macros.v" module Arbiter (REQ_, reset_, clk_in, frame_, irdy_, GNT_, adbus, cbe) parameter MASTERS = 6 //This code can handle a maximum of six masters.
Arbiter
- Arbiter unit includes client and server units. Used for Arbitation of multipliers in Altera FPGA based project. The code supports several multipliers and several clients with different priorities.-Arbiter unit includes client and server units.
PCI_BUS_ARBITER
- PCI仲裁器代码，用verilog硬件描述语言写的-PCI Arbiter code, written in verilog hardware descr iption language
arbriter-full
- this code is arbiter verilog design code and with testcases.
Backoff-verilog
- 一个简单的总线轮询仲裁器Verilog代码 -A simple bus polling arbiter Verilog code
arbiter
- A four level, round-robin arbiter WITH VHDL CODE
arbiter_ip
- Arbiter code for simulation purpose
arbiter-code
- this is design of an multimedia arbiter in vlsi with screen shots
arbitration
- arbiter code in verilog hdl
AHBArbiter
- AMBA ahb总线协议的arbiter模块源代码，verilog编写，适合新手学习使用。-this is a code of AMBA AHB arbiter protocol in verilog
arb
- arbiter code for dual ported ram
ahb_system_generator_latest.tar
- AHB system generator. This file is a part of a system generator for AHB system. it is VHDL code for the AMBA arbiter.