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mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
binarycount
- PROTEUS仿真PIC16F877的例子，是一个二进制的计数器-PROTEUS simulation PIC16F877 example is a binary counter
11
- cnt6.bdf 六进制约翰逊计数器 counters.vhd 不同功能的简单计数器 count60.vhd 60进制计数器 count60.bdf 60进制计数器 counter_1024.vhd 8位二进制计数器 counter_1m.vhd 16位二进制计数器 counter.vhd N进制计数器-M Johnson cnt6.bdf six different functions counters.vhd counter simple counter count
count_binary_0
- 二进制计数器的硬件代码，可在ISE或quartus下完成调试-Binary counter hardware code, available at ISE or Quartus to complete debugging
counter
- 详细描述n比特计数器及RTL验证，计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器，可以向上向下计数，并可设置计数值，计数器用异步的方式进行低电平复-A detailed descr iption of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter
counter
- It s a binary counter
Counter
- 所谓24进制计数器,要在数码管上直观的显示0,1…..22,23等数,再归零-The so-called binary counter 24 to the digital control on the visual display 0,1 ... .. 22,23 and a few, then zero
counter
- 任意多进制计数器，可以进行计数，制定进制数然后计数。也可以进行移位显示。-Any number of binary counter can count, then count the number of developing band. Shift can also be displayed
counter
- 这是带清零端的8位二进制计数器，是用verilog hdl语言编写的-This is the side with a clear 8-bit binary counter, is written with the verilog hdl
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal
counter
- N-bit binary counter using behavioral model
10-binary-counter
- 使用verilog实现10进制计数器功能,可以实现Quartus仿真，含任意进制计数器程序-10 binary counter using verilog implementation function, can realize Quartus simulation program with an arbitrary binary counter
8-jinzhi-counter
- 8进制计数器 每计数八次进一次位，vhdl语言的基础程序，对初学者很有帮助-8 binary counter into a bit of each of eight counts, vhdl language based program, very helpful for beginners
10-jinzhi-counter
- 10进制计数器 每计数十次有一个进位，是vhdl编程的基础程序，应用于fpga cpld可编程逻辑器件-Total scores of 10 binary counter has a per carry, is the basis for vhdl programming procedures used in programmable logic devices fpga cpld
design-a-decade-counter
- 设计一个四位二进制计数器，将计数结果由数码管显示，显示结果为十进制数。数码管选通为低电平有效，段码为高电平有效。-The design of a four-bit binary counter will count digital display, and displays the results as a decimal number. Digital tube strobe active-low segment code for active high.
VHDL-Binary-counter
- Binary counter, its used to count the numbers in binary format
binary-counter
- 此文件为Altium Designer Summer 09中二进制计数器的源程序，欢迎大家参阅。-This file Altium Designer Summer 09 binary counter source, welcomed everyone to see.
Binary-counter-experiment
- 利用NI ELVIS平台搭建电路，运用Labview编程，设计一个二进制计数器。-Use NI ELVIS platform to build circuits using Labview programming, design a binary counter.
Johnaon_counter
- 本设计为六位约翰逊(Johnson)计数器，首先给大家介绍一下什么是约翰逊计数器，它又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。它与环形计数器不同,后者用n位触发器仅可表示n个状态。2~n进制计数器(n为触发器的个数)有2~n个状态。若以6位二进制计数器为例,它可表示64个状态。但由于8421码每组代码之间可能有二位或二位以上的二进制代码发生改变,这在计数器中特别是异步计数器中就有可能产生错误的译码信号,从而造成永久性的错误。而约翰逊计数器的状态表中,相邻两组代码只可能有一位二进
bcd counter
- Binary counter design in verilog