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fdpll
- 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
5B6B
- FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or b
Design_of_a_6.25_Gbps_Backplane_SerDes_with_TOP-do
- SerDes自顶向下的设计方法流程，包括接收机、发射机、均衡技术、时钟恢复技术-SerDes top-down design methodology process, including receivers, transmitters, equalization, clock recovery techniques
shift
- E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuit
100Mbsyitaiwangshizhongshujuhuifudianlu
- 100以太网的时钟恢复电路，是涉及以太网的好资料，欢迎下载交流。-100 Ethernet clock recovery circuit, is related to Ethernet' s good information, please download the exchange.
5b6b
- 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输，串行码序列中连续的比特0或比特1的长度不超过5，数据在0和1之间变换的密度很高,并具有直流平衡的特性，有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conver
APL99
- An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery
A_method_based_on_Leo_satellite_communications_tim
- 摘 要:定时恢复是数字接收机中的关键技术,基于某特定LEO低轨卫星通信系统应用,重点研究了异步时钟采 样恢复法的工作原理,提出了一种改进的Gardner定时误差检测算法,给出了整个定时环路的具体实现方案,并针对其 性能进行了分析。仿真结果表明,在大多普勒加速度的卫星信道环境下,该方案能够满足系统设计的要求,且实现结 构简单、优化,可大幅降低算法复杂度,在较高信噪比的情况下,具有更加优化的性能。 -Abstract: The timing recovery is a key tec
Jitter-and-clock-recovery-for-periodic-traffic-in
- Jitter and clock recovery for periodic traffic in broadband packet networks
tdm_over_IP
- white paper on Jitter and clock recovery for periodic traffic in broadband packet networks
pll_clock
- 自己写的时钟提取逻辑。用于时钟恢复电路。-Write your own clock extraction logic. For the clock recovery circuit.
OFDM_retiming
- 基于Verilog的OFDM时钟恢复模块，在做全数字OFDM的时候是关键模块，可以在FPGA上实现。-Verilog-OFDM-based clock recovery module, doing all-digital OFDM time is the key module can be implemented on the FPGA.
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.
LMH0346
- 国家半导体的时钟恢复芯片LHM0346，双差分-National Semiconductor Clock Recovery Chip LHM0346
clcRec
- This a clock recovery matlab code. This file is using a 4-PAM signal shape and the recovery method is DD recovery method. This file is a mfile. -This is a clock recovery matlab code. This file is using a 4-PAM signal shape and the recovery method i
clcRecoveryDDmethod
- this file is implementing CLOCK recovery using DD method in matlab. This is a mfile. The signal shape is 4PAM
00231921
- digital implement Part II the Gardner method for clock recovery and synchronization
Digital-Clock-Recovery-Algorithm-for-Optical-Cohe
- We propose a digital clock recovery algorithm and demonstrate its tolerance to at least 5GHz laser frequency mismatch in a 43Gb/s DP-RZ-QPSK receiver after 1200km transmission.- We propose a digital clock recovery algorithm and demonstrat
four-channals-3.125G-SERDES
- 介绍SERDES接口中频率合成器和时钟恢复电路的设计-The first key issue is frequency synthesizer and clock recovery circuit design．
cdr
- 数据时钟恢复，采样8倍率高频时钟进行数据时钟恢复。已通过Modelsim仿真-Data and clock recovery, sampling 8 times the rate of high frequency clock for clock and data recovery. Have been through the Modelsim simulation