搜索资源列表
7seg_led
- 使用xilinx公司的FPGA实现了七段码的定时器时钟程序-use of the Xilinx FPGA in paragraph 107 of the Code timer clock procedures
clockbyvhdl
- 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
ClockDiv
- 本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
clock
- 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过
clock
- verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，
数字时钟管理器，xilinx公司开发板集成时钟
- 数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。-Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.
123654vhaing
- 八音自动播放电子琴设计 vhdl源码，文件内有具体注释 [VHDL-XILINX-EXAMPLE26.rar] - [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9- -Octave electronic keyboard play aut
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
06626_DLL
- XILINX的DLL的使用介绍，对于时钟的应用有很大的帮助-XILINX the use of the DLL, the application for the clock will be very helpful
clock_module_ref
- Xilinx clock module design
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
Xilinx_DCM
- 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
clock
- clock example for xilinx spartan 3 starter board-clock example for xilinx spartan 3 starter board....
clock
- XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the
dcm
- Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
digital-clock
- Digital clock applicatian using seven segment with fpga xilinx
clock
- verilog的数字钟代码，在XILINX上运行，可以手动设置时钟、闹钟，可报警-digital clock verilog code running on XILINX, you can manually set the clock, Alarm Clock, alarm
clock
- 使用xilinx公司的XC95288XL芯片来驱动2个数码管显示24小时时钟制。-Using xilinx s XC95288XL chip to drive two digital display 24-hour clock system.
clk-xlnx-clock-wizard
- Xilinx Clocking Wizard driver. -Xilinx Clocking Wizard driver.
gtx_aurora_zc706_clock_module
- 对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)