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卷积码译码器,采用sova算法译码-Convolutional Decoder, decoding algorithm used SOVA
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LogMAP译码算法,可用于递归卷积编码和非递归卷积编码的译码，代码质量高，供参考,<1> Log MAP decoder for RSC and NSC convolutional codes
<2> Based on Lalit Bahl s original BCJR algorithm and its logarithmic version (Hanzo & Woodard).
<3> Test-bench code is also inclu
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verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
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viterbi译码源代码,可以直接调用 The Viterbi decoder for convolutional codes-viterbi decoder source code, can be directly called The Viterbi decoder for convolutional codes
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卷积编码器和viterbi译码器的设计与仿真-Convolutional encoder and viterbi decoder design and simulation
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高质量Viterbi译码器,用于卷积码译码-High-quality Viterbi decoder for decoding convolutional codes
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卷积码的MATLAB实现，包括编码器和译码器。-Convolutional codes of MATLAB to achieve, including the encoder and decoder.
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FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation-Convolutional code encoder and Viterbi decoder design
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Matlab的卷积码译码器的设计与仿真的课程设计报告。-Matlab code of convolutional decoder design of the curriculum design and simulation of the report.
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Viterbi decoder for nonsystematic convolutional code. The encoder could be designed arbitrary through the generate matrix and parameter k. The number of row of generate matrix is output bits, and collom is constraint length. Parameter k is the number
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convolutional decoder implimentation
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Convolutional Encoder Viterbi Decoder Simulation in MAtlab
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卷积码编码器的实现，是误码性能分析的一部分-Implementation of convolutional encoder
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卷积码维特比译码器设计输出完整电路进行误码率分析-Convolutional code Viterbi decoder integrated circuit design of the output bit error rate analysis
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the rate 1/N convolutional encoder
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viterbi decoder with convolutional encoder
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编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
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Viterbi decoder, convolutional coder and some fig
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Convolutional Coding, Encoder, Decoder, C++ Implementation, With Self Document In Program Comments
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