搜索资源列表
CORDIC_ip
- cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined
cordic
- vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
Cordic123
- for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly-for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly
cordic_new
- Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation.-Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for
cordic_mpy_100722
- 6bit & 32 bit pipeline CORDIC 乘法器-6bit & 32 bit pipeline CORDIC Multiplier
cordic-verilog
- 用Verilog写的cordic相位鉴别，采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
cordic
- 用verilog实现的一个基于流水线结构的正余弦信号发生器，六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
cordic_atan
- 实现cordic vector模式 3级流水线 24级迭代-24 iterations of the three pipeline cordic vector mode
cordic
- verilog实现的cordic算法，经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
SINANDCOS-CORDIC
- 该资料是利用cordic算法实现正余弦函数计算输出的源程序及说明。资料中包含迭代算法和流水线算法。-This information is to use cordic algorithm source code and instructions cosine function calculates the output. Iterative algorithms and data contained in the pipeline algorithm.
Cordic-arithmetic-pipeline
- FPGA实现基于Cordic算法的流水线结构设计，相关verilog语言代码-FPGA to realize the Cordic code