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0下载：
用verilog HDL实现自相关算法！
RTL级可综合代码！
通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
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这是一个VERILOG接收端捕获模块，扩频码32倍，可以检测到相关峰-This is a VERILOG receiver capture module ,the spreader is 32,it can test the correlation peak
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QPSK相关接收机及匹配接收机的verilog实现-QPSK correlation receiver and matching receiver verilog implementation
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FPGA中将用采样点产生相关矩阵R的verilog代码-FPGA will generate correlation matrix R verilog code with the sampling points
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Verilog写的串口收发程序 ,基于FPGA的相关测试，亲测没有任何问题。-Verilog write the serial transceiver procedures, FPGA-based correlation test, pro-test without any problems.
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