用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!

FPGA中将用采样点产生相关矩阵R的verilog代码-FPGA will generate correlation matrix R verilog code with the sampling points