利用VHDL编写的一个简单的16位计数器-VHDL prepared using a simple 16-bit counter

外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.