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D触发器的设计
主要用在时序电路中。
所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
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verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a descr iption of the fringe is triggered D flip-flop, test test pass
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带置复位的D触发器的Verilog描述和仿真波形。-Reset the D flip-flop with set of Verilog descr iption and simulation waveforms.
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cnt_top,It is used to realize a D flip flop.
it is written with verilog.
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简单的D触发器的Verilog描述及，仿真波形-A simple D flip-flop in Verilog descr iption and simulation waveforms
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verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted
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Verilog and VHDL programs for sipo buffer,d flip flop etc
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带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
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D触发器，Verilog实现，配有实验说明文档。-D flip-flop, Verilog implementation, with experimental documentation.
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verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
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带同步清0、同步置1 的D 触发器 verilog语言描述的-0 with synchronous clear, synchronous set 1 D flip-flop verilog language descr iption
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带同步清0、同步置1的D触发器，可以实现D触发器-0 with synchronous clear, synchronous set 1 D flip-flop, D flip-flop can be achieved
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Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
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Verilog的简单D触发器设计-Simple D flip-flop in Verilog design
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Verilog code of D-Flip Flop
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FPGA VERILOG实现 D触发器 -FPGA VERILOG D flip-flop
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D触发器的Verilog硬件语言实现，开发环境是ModelSim-The D flip-flop of the Verilog hardware language development environment is ModelSim
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Useful verilog programs on various logical functions like D Flip-Flop, DSP butterfly unit, Multiplexers, etc.
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学习verilog时写的D触发器实验代码(D flip-flop experimental code written when learning Verilog)
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学习verilog时写的D触发器源代码，供大家参考(D flip-flop experimental code written when learning Verilog)
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