搜索资源列表
ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
leon3-altera-ep2s60-ddr
- The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor in
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
cpu-leon3-altera-ep2s60-ddr
- 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！
DDRinterface
- 《ALTERA FPGA/CPLD高级篇》高速DDR存储器数据接口设计实例
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
ddr_ddr2_sdram9.0
- altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
1
- PCIE 与DDR的接口范例，由altera提供-PCIE and the DDR interface examples provided by the altera
20060510191318991
- ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
DDR
- leon ep2s60 ddr use altera statix2 and add ddr sdram-leon ep2s60 ddr
AlteraCycloneIIFPGAStarterBoard
- Altera Cyclone II FPGA Starter Board原理图-Altera Cyclone II FPGA Starter Board Schematic
DDR_prj
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
DDR SDRAM Design Tutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
emb-dev-c3-appsel
- vhdl code for altera ddr design
DDR_CTRL
- DDR Verilog 控制器，quartus 10.1工程。适用Altera Cyclone® III starter board-DDR control quatrus 10.1，Altera Cyclone® III starter board
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
DDR_check
- altera公司cycloneII 2c35开发测试DDR的verilog代码，带仿真波形图。-altera cycloneII 2c35 verilog code development and testing DDR, with simulation waveform.
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
altera_ddr_verilog
- altera的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16，Verilog-The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog