搜索资源列表
ref-ddr-sdram-vhdl
- 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
ddr
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
cpu-leon3-altera-ep2s60-ddr
- 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！
DDR SDRAM控制器的VHDL代码已经测试
- DDR SDRAM控制器的VHDL代码已经测试
DDR_SDRAM_controller
- ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
ref-ddr-sdram-vhdl
- 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
testbench
- ddr sdram controller datd module source code
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
DDRctroll
- ddr 的fpga 控制器的实现 仿真正确-ddr controller fpga to achieve the correct simulation
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
DDR2_hardcore_userguide
- xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
ddr-sdram--chengxu
- ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
tips_vhdl
- 包含图像采集、i2c设计及混合语言仿真、DDR控制器以及一些小程序，供学习使用-Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use
ddr-sdram
- DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
ddr_contrl
- DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
DDRcontrol
- DDR控制器的设计参考，包含有中文说明文档-DDR controller design for reference, including documentation in Chinese
DDR_prj
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
ddr
- DDR SDRAM 控制器 VHDL代码，可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus