有VHDL写的一个38译码器,并付仿真波形.-VHDL has written a decoder 38, and pay the simulation waveform.

加减计数器 library ieee use ieee. std_logic-_1164.all entity dec3_8 is port(a,b,c,s1,s2,s3: in std_logic y: out std_logic_vector(0 to 7)) end architecture b of dec3_8 is signal abc: std_logic_vector(0 t