搜索资源列表
div
- div的verilog开发程序，做稍微修改就可以应用到具体的工程当中
alu-div
- 用verilog HDL代码编写的快速除法器，比较有用
div.rar
- 除法器实验 verilog CPLD EPM1270 源代码,Experimental divider verilog CPLDEPM1270 source code
float_div_verilog
- 浮点格式遵循 IEEE754 标准。verilog设计源代码。-float point div . in verilog design.
div
- verilog任意分频电路实现，仿真效果非常好-div dclk
div
- 实现了不恢复余数除法器，采用Verilog HDL编码，仿真通过。-Not to restore the balance achieved divider, using Verilog HDL coding, simulation through.
clk_div
- 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
div
- 利用Ｖerilog实现定点数的除法，在此基础上可考虑实现定点数的除法-Using Verilog to achieve set division points, on this basis can be considered fixed points of the division to achieve
div
- VERILOG除法器，已经调试好。大家可以参照学习.-sub-divided function,I have debug it right.It is helpful to you
div
- 32位整数阵列除法器，verilog代码编写，性能高效。-32-bit integer array divider, verilog coding, performance and efficient.
div
- restoring divider in verilog
Div
- 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
div
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
VerilogFreq-div
- Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法-Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide
div
- 这是我用verilog写的一个电平触发的一个除法器，文件在压缩包内，开发环境是Quartus II。-this is a file of divide using verilog language.
DIV
- 用verilog语言设计分屏器，本程序分为两部分，一个可以实现任意奇偶分频的设计，一个可以实现任意半整分频的设计-Split screen using verilog language design, this procedure is divided into two parts, one can achieve arbitrary parity crossover design, one can achieve arbitrary dividing half the whole design
div
- FPGA的IP核中除法算法的源代码，是Verilog语言的，易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
div
- 使用quartusII软件，Verilog语言编写的一个分频器，仿真测试通过- frequency dividing circuit
New folder
- clock div testbench design and frquency division
div
- 运用verilog语言实现将频率分为二倍的作用。(two divided-frequency)