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actel-fpga-double-port-ram
- 基于Actel FPGA的双端口RAM设计--周立功单片机-Actel FPGA-based dual-port RAM design- ZLG MCU
dual_ram
- FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
dual_port_ram
- 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
ram_of_Fusion
- Fusion中的双口RAM编写，可以实现双向的调用。用Verilog编写。-Fusion in the preparation of dual-port RAM, you can realize a two-way call. Prepared using Verilog.
TopLevel_DualPort_Ram_XilinxCore
- Top Level Dual Port Ram Core Project, VHDL code
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
FPGA-TWO-RAM
- 这样就可以在FPGA内实现双口RAM了-This can be achieved in the FPGA dual-port RAM
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
DP_RAM_lab
- 用SmartGen 生成一个2k*8 Dual Port RAM，并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger displ
dual-ram
- 实现双口RAM映射到DSP地址单元空间中，使得双口RAM直接读取DSP中的数据或程序。-Achieve dual-port RAM modules mapped to the DSP address space, making dual-port RAM directly read the data in the DSP or procedures.
ram
- 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
planta_fagner
- is a test of a verilog implementation to do a oscilloscope with dual-port RAM
TESTRAM
- FPGA，双口RAM测试程序，仿真双口RAM工作时序，对时序的理解！适合对双口RAM不太了解的初学者使用！QUARTUSII8.0软件平台仿真通过！-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much
dpRam1
- Dual port ram design project developed in Xilinx using VHDL
dualportram_asch
- This an asychronous dual port ram-This is an asychronous dual port ram
DUAL-PORT-RAM
- vhdl使用双口RAM，工程编译通过。编译工具QUARTUS 9.0。-vhdl using the dual-port RAM, compiled by engineering.
dual-port-RAM
- 利用MegaWizard设计一个双端口RAM-Use MegaWizard design of a dual-port RAM