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h264 Verilog
- h264 Verilog,用fpga实现基本档次功能。
hardh264
- 一个硬件H264编码的VHDL源码，用于FPGA开发，适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过，但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
bluespec-h264_latest.tar
- h264 vhdl/verilog implementation on FPGA platform
CAVLC
- H.264 CAVLC硬體原始碼下載，內附測試檔案。-H.264 CAVLC Hardware Verilog source code
JointwaveE460
- jointwave公司的h264编码方案，可实现1080P30，运用在FPGA/ASIC设计-jointwave h264 encoding scheme can be realized 1080P30, the use of FPGA/ASIC design
Design-and-Implementation-of-H.264
- 基于FPGA的H264编码系统设计与实现-Design and Implementation ofH.264 Encoding System Based on FPGA