一份很好的数字时延程序（采用farrow算法），采用Verilog HDL，经过测试通过，是我一个雷达项目中的代替模拟时延的。精度很高，并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation

用 Farrow 结构滤波器对并行采样信号进行时间误差校正, 通过 DSPBuilder 软件将设计的滤波器模型转化为硬 件语言, 利于 FPGA 实现-The Farrow filter is used to correct the time error of the parallel sampling signal, and the designed filter model is converted to hard by DSPBuilder software