i2c slave,这个是I2CBUS接收端的源代码，由VERILOG写成，经过综合和调试

I2C从设备（Slave） Verilog 代码、设计文档和使用文档，简单、适用：很方便修改工作频率，自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.

i2c从机可综合verilog代码，并包含简单主机，寄存器组。-i2c slave synthetic behave verilog code, including simple master and registers.