搜索资源列表
iic_master
- it is a iic source verilog code with its testcase which can act only as master
EEPROM
- VHDL语言写的IIC实现EEPROM，很好的程序，已经用过，没有问题-Written in VHDL language IIC achieve EEPROM, good procedures are used, there is no problem
iic_verilog
- iic 程序 用verilog语言编写，可以直接使用-iic program using verilog language, can be used directly