搜索资源列表
3Channel_CIS_Processor_with-VHDL.ZIP
- This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by
conv5x5_matlab_jtag_XUP_hw_in_loop
- Xilinx MATLAB、SysGen的 图像 DCT工程-Xilinx MATLAB, SysGen image DCT works
Fingerprint_Identify
- 本项目名称是：基于FPGA的指纹识别模块设计。 主要内容为：本模块采用xilinx公司的Spartan 3E系列XC3S500E 型FPGA作为核心控制芯片，通过富士通公司的MFS300滑动式电容指纹传感器对指纹图象进行提取，然后对提取的指纹图像进行灰度滤波、图像增强、二值化、二值去噪、细化等预处理，得到清晰的指纹图象，再从清晰的指纹图象中提取指纹特征点，存入外部FLASH作为建档模板。指纹比对时，采用同样的方法获得清晰的指纹图像，建立比对模板，然后将比对模板与建档模板利用点模式匹配
video_capture_rev_1_1
- 视频图像的捕捉系统的实现，主要是基于XILINX系统的实现-Video image capture system implementation is mainly based on XILINX System
VGA_RefComp
- The VGA Reference Component 基于Xilinx SPARTAN-3E开发板-The VGA Reference Component generates the signals to display an image on a standard VGA display. It can manage both 640x480 and 800x600 resolutions and is compatible with both CRT and LCD displ
Mathematical-Operation-of-image-pixel-using-XSG.r
- mathematical opering using xilinx system generator
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
OZ745
- 4k*2K zynq The OZ745 is a video development platform based around the Xilinx® Zynq-7045 FPGA. The kit includes all the basic components of hardware, design tools, IP, pre-verified reference designs and Board Support Package to rapidly devel
imageprocess
- 典型的图像采集verilog代码，开发板源码-this is typical image process code,provided by xilinx developmentpacadge
Xilinx_FPGA_FFT_Application_Note
- Xilinx FPGA中FFT IP核的使用笔记，内部有FFT硬核的端口说明和具体设置以及源代码，对于数字信号处理研究人员，能图像处理、雷达成像、实时通信开发人员较多的开发时间！-Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port descr iption and specific settings as well as the source code for digital signa
Puzzle
- 一个用verilog编写的VGA显示拼图游戏，本程序基于Xilinx的Basys2开发板，图像存储于ROM中-A VGA display jigsaw puzzle with verilog written, the program is based on the Basys2 Xilinx development boards, the image is stored in ROM
CONVERT
- This scr iptconvert a image to coef values for ip core block ram generator xilinx
hdmi_20130227
- (1)包含驱动HDMI编码芯片Sil9134的时序逻辑和寄存器初始化代码，输出测试图像格式为1080P@30Hz；（2）使用Vivado2013.3开发，硬件平台为威视锐Zing开发板，搭载Xilinx Zynq7020芯片。-(1) contains drivers HDMI encoder chip Sil9134 timing logic and register initialization code, output test image format 1080P @ 30Hz (2)
LogiCORE-IP-Video-Scaler-v4.0
- The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.
06168353
- The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the very vital applications of the fast fourier transform include Signal analysis, Sound filtering, Data compressio
FPGA-based-image-median-filtering
- 基于FPGA的图像中值滤波，在xilinx的FPGA上实现了算法，采用matlab的算法最终通过了验证。-FPGA-based image median filtering on xilinx FPGA implementation of the algorithm, using matlab algorithm finally passed validation.
bram_shift_reg_w16x3072
- 使用 xilinx blockram 做连续shift 在图像处理中 做多行缓存很方便-Using blockram Xilinx as a continuous shift in the image processing to do more than the cache is convenient
verilog-image-decompressor-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
vsmkq
- Particle image segmentation and matching subroutines themselves are prepared, Is the topic of the elementary school stage curriculum design, High-resolution array signal processing estimates.