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这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
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This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
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根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can a
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1/3,k=9的卷积码VHDL实现,在xilinx ise上仿真成功。-1/3, k = 9 convolutional code VHDL implementation of the simulation in the xilinx ise success.
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In this case is a interleaving algorithm code for deinterleaving the code, using VHDL language. This code provide the method of interleaving of the convolutioned code
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