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ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序,使用Verilog,调用MIG,编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH,无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
Xilinx_DDR
- 本文档对ISE开发环境利用MIG调用DDR2 IP CORE进行了进行了详细的介绍,对初学者很有帮助。其中FPGA芯片为Xilinx公司SP6 FPGA, DDR2 内存为Micron 公司的一款 R2 MT47H128M8 芯片。-This document calls ISE development environment using MIG DDR2 IP CORE conducted a detailed descr iption, very helpful for beginners.
DDR2_Control
- 参考例程之Verilog之实现DDR2时序控制实现,ISE开发平台完整工程(Implementation of DDR2 timing control implementation of reference routine Verilog, complete engineering of ISE development platform)