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fullsine
- This a code for sine wave generation in modelsim. The code is written in verilog. An lut has to be added to this program to work completely.-This is a code for sine wave generation in modelsim. The code is written in verilog. An lut has to be added t
lut_core
- lut core in vhdl program
atan_lut
- atan lut in vhdl program
FIR-FILTER
- FIR filter lut based in vhdl