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washingmachine.rar
- 采用步进电机模拟洗衣机电机，实现上水、浸泡、洗涤、漂洗、甩干等过程。洗涤分弱洗、轻洗、强洗；可设定3级水位设定，每级水位均设定水位下限（值自定）；可选择漂洗次数（3～5次）。使用键盘进行流程及参数设定及自动存储流程，有停止键终止洗衣机的工作，并在LED或LCD上显示当前流程。,Full-automatic washing machine controller design.
LCD.rar
- 有限状态机的设计——LCD显示控制实验，用VHDL编写程序，整片报告,Finite state machine design- LCD display control experiments, using VHDL programming, the whole report
fsm
- 有限状态机工作原理、设计方法、步骤等精要说明-Finite state machine working principle, design method, such as Essentials of steps to explain
state-machine-design
- 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog learners
Cadence.doc
- 在PC机上运行cadence需要先运行命令:source filename,此处filename指.cshrc,或其他具有该文件内容但名字不同的文件,该文件必须有set DISPLAY 本机IP:0.0 语句,同时应将其他雷同设置封住.可以先从工作站上下载.cshrc文件,然后用notepad修改显示设置相,不可用其他编辑器,否则文本文件格式会不一样.记住,必须将显示器设置为256色.-In the PC machine running cadence need to run the comma
+VHDL
- 很详细用VHDL写的自动售货机程序有详细的说明和设计要求实现功能-Very detailed written using VHDL vending machine procedure is described in detail and design requirements for the realization of function
VHDL
- 各种有限状态机的设计。 VHDL源代码。 -All kinds of finite state machine design. VHDL source code.
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
virtual_machine_design
- 虚拟机的设计与实现-C_C++光盘资料.rar-Virtual Machine Design and Implementation-C_C++ CD-ROM. Rar
inductioniseq1
- induction machine design progrAM
Simulation-washing-machine-code
- 这是一个模拟洗衣机模型的设计代码，每段都有很好的注释，希望对你有所帮助。-This is a simulation model of washing machine design code, each has a very good note, I hope for your help.
Wordware-Publishing-Virtual-Machine-Design-and-Im
- C++ E-Books Tutorials Wordware Publishing Virtual Machine Design and Implementation in C++ - rar
state-machine-design
- Verilog and VHDL状态机设计，内含源代码，希望对大家有所帮助。-Verilog and VHDL state machine design, including source code, we want to help.
machine-design-
- 状态机实现序列检测器的设计，了解一般状态机的设计与应用-State machine to implement sequence detector design, understand the general state machine design and application
Virtual-Machine-Design
- 虚拟机的设计与实现：C/C++ 电子书 扫描版-Virtual Machine Design and Implementation-C/C++ Document
complex-model-of-the-machine-design
- 一份完整的复杂模型机设计与实现的报告，详细写明了数据格式以及指令格式，另外还有实验步骤及系统测试。-A complete complex model of the machine design and implementation, specifying the data format and instruction format, in addition to the experimental procedures and system testing.
Finite-state-machine-design-part
- VHDL语言 有限状态机交通灯的设计 有限状态机设计部分-VHDL language finite state machine design of traffic lights finite state machine design part
State-machine-design-techniques
- 状态机设计-英文-如何编写状态机-case-State machine design techniques for Verilog and VHDL
State MAchine design for FPGA
- FPGA state machine design.
finite-state-machine-design
- 单片机有限状态机的设计技术相关文章资料，状态机设计可以降低循环时间-finite state machine design technongy