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目前以太网PHY芯片是通过总线MDC/MDIO
- 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
LPC176x-web
- keil 源文件，包含tcpip协议栈,easyweb sever-This project is migrated from Keil MCB1700 Demo code. It can run at Keil MCB1700 board with LPC17xx. Example functionality: - Clock Settings: - XTAL =
MDIO
- The MDIO interface is a simple, two-wire, serial interface, clock and data. MDIO is used to connect a management entity and a managed PHY for the purposes of controlling the PHY and gathering status from the PHY. The two lines include the MDC lin
IEEE-P802.3ae-MDC-MDIO
- explain MDIO protocol
SVN-52
- AC101网络驱动程序，里面包含相当详细的注释，且使用GPIO模拟MDIO、MDC等接口-AC101 network driver, which contains quite detailed notes, and use the GPIO analog MDIO, MDC and other interfaces
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
mdc
- 实现对MDIO通信接口的MDC主机时钟进行整形，输出占空比50 的时钟方波-MDIO communication interface to achieve the MDC host clock shaping, the output duty cycle of 50 of the clock Fang Bo