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vhdlcodes
- with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,electronic voting machine,mod 16 counter,jk flip flop.please accept these codes and make me member of this site.so that i can download code from this s
cnt8
- 用JK-flip-flop做的8进制counter-mod-8-counter
counter_advanced
- A counter that starts from 0 and increments mod 16 on each rising edge of the clock
mod10asynchro
- this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
mod6asynchro
- this is a code for mod-6 asynchronous counter in verilog.
shiziluoji
- 三位二进制加1与加2计数器 ：三位二进制模5计数器。当外部输入X = 1时，计数器加2计数；外部输入X = 0时，计数器加1计数。“模5”为逢“5”进1计数。 原始条件：使用D触发器( 74 LS 74 )、“与”门 ( 74 LS 08 )、“或”门( 74 LS 32 )、非门 ( 74 LS 04 )，设计三位二进制模5计数器。 -The three binary counter plus 1 and plus 2 : three binary mod 5 counter. X =
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal
mod_6counter
- its a mod 6 counter designed using structural modelling
04301090a-u-law
- mod 16 counter using vhdl
New-folder
- most example dff,tff,jk,mod,clock,factorial,counter,array,sum 10....many more
MetahookEngine0.2
- This a source for counter-strike 1.6. We can make mod like CSO with this code.