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8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
ModelSim_SE_tigeress359617728
- modelsim十分钟入门——初学者很容易上手-modelsim 10 minutes portal -- beginners can easily drop
risc_cpu
- 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this e
Modelsim 10.0 turtuil
- Modelsim 10.0 turtuil
ISE7.1
- ise 中文使用手册，详细介绍如何使用ise，附大量图片说明-ise Chinese user manual details how to use the ise, attached to a large number of captions
Xilinx_FPGA
- 介绍了FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE-Introduced the entire FPGA design process: Modelsim>> Synplify.Pro>> ISE
code
- 代码文件夹： ARVI_FSM.v为顶层文件，用于模拟时用。 dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB） dataFormat.dat为输入文件对应的带格式的文件 使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt 结果: result.txt -Code folder: ARVI_FSM.v for top-level documen
50973937-VHDL-Report
- Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For s
XILINX-ISE-MODELSIN-SE-Simulation
- Modelsim 10.0a 中建立 Xilinx ISE 13.1的仿真库及其之间调用设置详解。-Modelsim 10.0a create Xilinx 13.1 calls between the simulation library and its setting Detailed.
Verilog
- 设计一个自动售货机，此机能出售1元、2元、5元、10元的四种商品。用于modelsim verilog 语言的编写-To design a vending machine, this function is the sale of 1 yuan, 2 yuan, 5 yuan, 10 yuan of the four commodities. The sale of what kind of goods to the customer pressing a button and digital
test-pwm
- FPGA 生成PMW波及其测试程序 使用modelsim se版本10.0测试可用-The FPGA generates the PMW wave and its test program
modelsim-
- modelsim 10.0a 破解,主要用于modelsim 10.0a 破解-modelsim 10.0a crack, mainly for modelsim 10.0a crack
counter10
- verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
modelsim-se-10.1a-crack
- modelsim10.1a的破解文件，已测好用，破解简单-modelsim10.1a crack file, have been measured easy to use, simple crack
modelsim-se-10.1a-crack
- modelsim se 10.1a emouse的破解文件，亲测好用，里面说明详细-modelsim se 10.1a emouse crack
8-bit-RISC_CPU
- 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
sequence-detector
- 3比特的任意二值序列检测器，Quartus 10.0+modelsim 6.5SE联仿真报告形式-3 bits of arbitrary binary sequence detector,simulation with Quartus 10.0+ modelsim 6.5SE，report forms
modelsim se 10.1a crack
- Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation
crc7
- 以crc7为例进行UVM的验证 Part 1： 搭建环境。 本文使用的Quartus II 13.1（64 bit），器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是，没找到Modelsim自带的uvm_dpi.dll，于是，还重新编译了一番。 本文在win 10下。下载uvm-1.1d（现在最新版本有1.2d了），放好。(crc7 code by system verilog language)
Modelsim 10.2c
- Crack of Modelsim 10.2c