搜索资源列表
booth_multiplier
- Booth multiplier written in verilog
32_bit_complex_multiplier
- 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
multi16
- verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
WallaceTreeMultiplier
- Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language
booth
- booth multiplier in verilog, deisgn in parameterized.
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
MAC
- Multiplier/Accumulator written in Verilog
CourseDesign
- 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
booth
- 一个booth乘法器的小例子, 有助于理解booth算法-An example for a booth multiplier in Verilog HDL
multiplier
- paralel multiplier in verilog
mul
- multiplier in verilog
multiplier
- this source code is one example to build multipler in verilog HDL.
Floating-Point-Multiplier-in-Verilog
- Floating Point Multiplier in Verilog
booth
- booth multiplier in verilog
multiplier
- 8 bits multiplier module in verilog a[7:0]*b[7:0]=c[8:0] // only use one adder
complex-mul
- complex multiplier in verilog code is uploaded
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
serial_multiplier
- Module for Sequential multiplier in verilog