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P4_PPC_SDRAM_Reference_Design
- SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief descr iption of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller ·
my_zbt_controller
- ZBT内存控制器.支持OPB总线。VHDL源码
opb_wb
- 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信， 从而使用基于Wishbone的许多开源IP Core
opb_psram_controller.tar
- opb接口sdram控制器源码，标准参考设计，verilog语言
opb_vga.EDK下的用户IP核
- 一个EDK下的用户IP核，进行OPB总线到VGA的转换,EDK under a user IP core, the OPB bus to VGA conversion
opb_lcd_controller_v1_00_a
- spartan3系列fpga opb模式下lcd液晶屏控制代码-spartan3 Series fpga opb mode lcd LCD screen control code
MicroBlazeprocessors
- 利用 OPB 定制外设连接 LCD 和 MicroBlaze 处理器-Custom OPB peripheral connectivity using LCD and MicroBlaze processors
mbtutorial
- This tutorial guides you through the process of using Xilinx Embedded Development Kit (EDK) software tools, in which this tutorial will use the Xilinx Platform Studio (XPS) tool to create a simple processor system and the process of adding a cust
Developing_GUIs_in_C++
- we’ve successfully developed a simple GUI interface, using only a few lines of code. The major factor which works here is the entire class structure is re-usable, and can be applied to build a lot of other different User Interfaces too. The reader c
xapp913
- Reference System: OPB CAN Controller
mylcdip
- lcd vhdl ip 核 挂接在 opb 总线上 可以完美实现 lcd 字符液晶的 驱动。-this is a vhdl lcd character ip core based on OPB （onchip periheral bus）
mkjpeg.tar
- 用FPGA实现的JPEG编码器，可以直接使用，内含完成说明文档，经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • T
lecture9
- The OPB Bus and IPIF Interface Cores-The OPB Bus and IPIF Interface Cores