搜索资源列表
ethernet.tar
- 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
CRC
- 这个是我花了一个星期的CRC算法，有并行与串行的区别与时序的分析。。。。希望站长能够同意-This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
crc16
- CRC16的源程序，实现crc校验，并行crc校验-CRC16 source, the realization of CRC checksum, parallel CRC Checksum
CRC
- 本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并 行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating differ
CRC_16
- crc16的串行和并行写法，而且有详细的测试文件-Serial and parallel crc16 written, and detailed test documents
Crc_Parallel
- CCITT Parallel CRC 16-bit
crc
- 高速多通道crc实现，可以并行实现5个通道数据的校验，支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard
crc
- crc串,并行算法:穿行算法实现循环冗余校验码的编码 并行算法实现循环冗余校验码款速编码.-crc serial, parallel algorithms: walk through algorithm encoding cyclic redundancy check code parallel algorithm for cyclic redundancy check code section rate coding.
parallel_CRC_code
- CRC Generation can be done by using PARALLELISM. Efficient method to calculate CRC in less time. By using more hardware for parallel CRC and obtaining more latency and throughput.
eth_crc
- crc校验码Verilog 程序。此为4位并行crc——32校验。-crc checksum Verilog program. This is a 4-bit parallel crc- 32 check.
UHF-RFID-CRC
- 本文首先研究了IsO／IECl8000．6标准中A、B两类短程通讯的前向链路与返回 链路的数据编码方式，对(FMO)双相间隔编码、(PIE)脉冲间隔编码、曼切斯特码 的编解码方式和技术参数进行了深入的分析，并利用FPGA实验平台对这三种编 码的编、解码电路进行了设计和仿真。然后对UHF RFID系统的差错控制技术原理 进行了探讨，重点研究了ISo／IECl8000．6标准中采用的数据保护与校验技术，即 循环冗余校验(CRC)技术。分析了基于线性反馈移位寄存器(LFSR)实现C
CRC-calculation-principle
- 这是一篇论文，通用并行CRC计算原理及其硬件实现方法-CRC calculation principle of universal parallel hardware implementation
CRC-Parallel-Computation
- 用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
CRC-8
- VHDL code for CRC-8 computing using 32 bit input (parallel)
CRC
- 包括按位完成crc运算和按字节并行处理完成crc运算。经测试可以顺利实现编码和解码，功能完美-Bitwise crc computing and parallel processing to complete byte crc computing. Has been tested the smooth realization of the encoding and decoding, perfect function
parallel-CRC-calculation-in-FPGAs-
- 给大家介绍关于crc校验原理和算法。并在fpga实现描述。-To introduce the crc check principle and algorithm。To achieve the descr iption in fpga
crc_tool
- 用c编写的自动生成并行crc处理的verilog代码的工具-Automatically generate the verilog code to parallel crc processing tools written with c
CRC
- CRC检验以及并行校验源代码基于veriloghdl-CRC check and verify the source code is based on the parallel veriloghdl
CRC
- FPGA中并行实现CRC-CCITT标准的循环冗余校验码的生成-FPGA to achieve CRC-CCITT standard parallel cyclic redundancy check code generation
crc
- 并行循环冗余校验码的生成模块和检验模块，quartus仿真-Generate and test modules in parallel cyclic redundancy check code