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pc_cfr_v2_0_msim_r2_0
- Xilinx公司pc_cfr IP核的MatLab仿真-matlab simulation model of pc_cfr ip core of xilinx
pc_cfr_v3_0_bitacc_cmodel_nt64
- In Low-IF receiver architecture all the RF signals are translated to low-IF frequency which is then down-converted to BB signal in digital domain. Low-IF architecture comprises the advantages of both heterodyne and homodyne receivers