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6-portRegisterFile
- 6端口寄存器IP内核VHDL源代码，所需的开发环境是QUARTUS II 6.0。
quartus6.0
- Atlera 公司的开发软件平台quartus 6.0的license
Sinout
- dds正弦可控发生计全结果 用到matlab，dsp，Quartus II 6.0软件-dds controllable sinusoidal occurred wholly the result of use of matlab, dsp, Quartus II 6.0 software
VGAdisplay
- VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 芯片EP2c8Q208-VHDL entry experiment. 256-color VGA display driver development software Quartus II 6.0 chip EP2c8Q208
word
- Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scroll
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
clock
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
musicplayer
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
caidengkongzhiqi
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
trafficlight
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
Crack_patch_license
- Quartus II 6.0 破解补丁和license设置-Quartus II 6.0 crack patch and license settings
Cymometer
- Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
Altera_Quartus_6.0_crack
- fonctional crack of VHDL describer Quartus 6.0
tutorial
- quartus ii 6.0版本tutorial文件，在不同的版本中会出现不同的说明介绍，包括6.0/ 7.2/ 8.0。-tutorial for quartus ii 6.0 that illustrate a quiker way to get access of basic feature of the design software
Quartus
- quartus简介6.0版，学习的好帮手-quartus 6.0 Introduction
DA
- 基于EP1C6Q240的DA转换程序代码，简单易懂，调试通过，基于quartus 6.0-The DA conversion based EP1C6Q240 code, easy to understand, debug through, based on quartus 6.0
Crack_Altera_6.0-9.1
- DSP builder6.0-9.0和quartus ii6.0-9.0等版本的破解器，注意运行破解器时最好关闭杀毒软件，否则有可能会出错-DSP builder6.0-9.0 and quartus ii6.0-9.0 and other versions of the cracker, pay attention to when the best off running the cracker antivirus software, or they may be wrong
clock_for_6.0
- 基于FPGA的电子钟，开发环境是Quartus II 6.0。功能是3个按键分别设置时分秒。通常作为课程设计，供同学参考~-Electronic bell, development environment based on FPGA Quartus II 6.0. The function is the three buttons to set the hour, minute and second. Usually as courses designed for students to ref
Quartus2-User-Manual-6.0
- Quartus 2使用说明，此为简单版本，贡查一般工作使用-Quartus 2 instructions for use, this is the simple version, check the general working tribute Use
VHDL程序
- 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)