This a simple vhdl code that perform division using the non restoring algorithm which is often handy-This is a simple vhdl code that perform division using the non restoring algorithm which is often handy

可复原算法：可复原算法通过在连续的被移位的被除数减去除数累加得到余数-Restoring Division Algorithm

Digital logic, basic combinational logic:adder, subtractor,multiplication and division(restoring, non restoring)

Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register is set to zero. In the second a