搜索资源列表
risc cpu
- 一个很好的16位cpu ip内核，用quartus写的
freerisc8_11.zip
- 8位RISC CPU的VERILOG编程 SOURCECODE,8 RISC CPU VERILOG programs SOURCECODE
cpudesign_doc.rar
- RISC cpu设计的经典教程，牛人讲义哦。,RISC cpu classic design tutorials, cattle were handouts Oh.
RISC_8.rar
- 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。,Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
CPU
- 八位简单risc cpu 设计的源代码，VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
RISC
- hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
32bit_RISC_CPU
- 32 risc cpu的参考设计，内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
risc
- 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
risc1200
- risc cpu设计源码，全部资料 欢迎下载-risc cpu core
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
alu
- this is source code in verilog for arithmatic logic unit for RISC cpu
RISCcpu
- this verilog model of RISC CPU-this is verilog model of RISC CPU
risc_cup
- 精简指令集CPU的VERILOG语言实现，很有用-RISC CPU the VERILOG language, very useful
32-bit-RISC-CPU-ARM
- 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM chip application and selection
RISC-CPU-ARM
- 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM chip application and selection
RISC-CPU-design
- 16位RISC-CPU设计，高四位为操作码，低12位为地址，寻址空间位4KB。包含12条指令（预设16条指令），3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the thre
RISC-CPU
- 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains