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RS232串口通信协议
- RS232串口通信协议，verilog实现，通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
rs232
- fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
uart01
- 一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序-A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
RS232
- RS232的FPGA通讯程序，用的是VHDL语言写的，非常好用-RS232 communication program of the FPGA, using the VHDL language, very easy to use
altera-schemic-
- FPGA应用，Altera的FPGA开发板原理图汇集，FPGA最小系统，rs232串口转换，VGA显示-FPGA applications, Altera' s FPGA development board schematic pooling, FPGA minimum system, rs232 serial converter, VGA display etc.
rs232
- 通过FPGA实现串口通信，结果在超级终端可见-Serial communication through the FPGA, the result can be seen in the HyperTerminal
screen_shoot
- Example of a screen shot module in a FPGA (upload bitmap file by RS232)
c_FPGA
- RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
RS232(1)
- 基于FPGA的串行通信接口设计，用硬件描述语言VHDL实现-FPGA-based serial communication interface design, using hardware descr iption language VHDL implementation
rs232
- 在FPGA上实现数据的串口传送，可以和上位机进行数据的首发，里面包含的仿真过程-Realized in the FPGA serial data transmission, data can be the starting PC, which contains the simulation
rs232
- 用vhdl实现fpga串口通信 包含 波特率生成 发送模块 接收模块 过采样 signaltap使用-Vhdl fpga serial communication with the realization of sending module contains the baud rate generation receiver module using oversampling signaltap
RS232
- simple example for uart on fpga
RS232
- RS232 串口通信 的 VHDL描述，初学FPGA的朋友可以-RS232 serial communication VHDL descr iption, FPGA beginner friends can see
RS232
- EP2C8Q208_Quartus_V8.0 基于FPGA实现RS232 VHDL代码-EP2C8Q208_Quartus_V8.0 FPGA-based implementation RS232 VHDL code